000			01950 a2200445 4500
001			57000
999			_c57000 _d14375
003			TR-AnTOB
005			20200624101624.0
008			061124s2006 ne a b 001 0 eng
010			_a2006006869
020			_a0123705975 (hardcover : alk. paper)
020			_a9780123705976
035			_a(OCoLC)ocm64624834
040			_aDLC _cDLC _dBAKER _dC _dIXA _dDLC
041			_aeng
042			_apcc
050			_aTK7874.75 _b.V58 2006
090			_aTK7874.75 .V58 2006
245		0	_aVLSI test principles and architectures : _bdesign for testability / _cedited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen.
264		1	_aAmsterdam ; _aBoston : _bElsevier Morgan Kaufmann Publishers, _cc2006.
300			_axxx, 777 p. : _bill. ; _c25 cm.
490	0		_aThe Morgan Kaufmann series in systems on silicon
504			_aIncludes bibliographical references and index.
650		0	_aIntegrated circuits _xVery large scale integration _xTesting _929454
650			_aEntegre devreler _xÇok büyük ölçekli entegrasyon _xTasarım _9127690
650			_aIntegrated circuits _xVery large scale integration _xDesign _9127689
650		0	_aEntegre devreler _xÇok geniş ölçekli tümleşim _xTest etme _929456
700			_aWu, Cheng-Wen, _cEE Ph. D. _929451
700			_aWang, Laung-Terng _929452
700			_aWen, Xiaoqing _929453
856		4	_uhttp://www.loc.gov/catdir/toc/ecip069/2006006869.html _3Table of contents
857		4	_uhttp://www.loc.gov/catdir/enhancements/fy0632/2006006869-d.html _3Publisher description
901			_0017158
902			_aGT
906			_a7 _bcbc _corignew _d1 _eecip _f20 _gy-gencatlg
925		0	_aacquire _b2 shelf copies _xpolicy default
955			_djf17 2006-02-27; _ejf17 2006-02-27 to Dewey _fld11 2006-10-02 Z-CipVer _gld11 2006-10-02 copy 1 & 2 to BCCD
942			_cBK