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999			_c200457356 _d75568
003			TR-AnTOB
005			20231114145708.0
007			cr nn 008mamaa
008			210802s2022 sz | s |||| 0|eng d
020			_a9783030797744
024	7		_a10.1007/978-3-030-79774-4 _2doi
040			_aTR-AnTOB _beng _erda _cTR-AnTOB
041			_aeng
050		4	_aQA76.9.A3
072		7	_aUKM _2bicssc
072		7	_aTEC008010 _2bisacsh
072		7	_aUKM _2thema
090			_aQA76.9.A3EBK
100	1		_aWijtvliet, Mark. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
245	1	0	_aBlocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures _h[electronic resource] / _cby Mark Wijtvliet, Henk Corporaal, Akash Kumar.
250			_a1st ed. 2022.
264		1	_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2022.
300			_a1 online resource
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction -- CGRA background -- Concept of the Blocks architecture -- The Blocks framework -- Energy, area, and performance evaluation -- Architectural model -- Case study: the BrainSense platform -- Conclusion.
520			_aThis book describes a new, coarse-grained reconfigurable architecture (CGRA), called Blocks, and puts it in the context of computer architectures, and in particular of other CGRAs. The book starts with an extensive evaluation of historic and existing CGRAs and their strengths and weaknesses. This also leads to a better understanding and new definition of what distinguishes CGRAs from other architectural approaches. The authors introduce Blocks as unique due to its separate programmable control and data paths, allowing light-weight instruction decode units to be arbitrarily connected to one or more functional units (FUs) over a statically configured interconnect. The discussion includes an explanation of how to model architectures, resulting in an area and energy model for Blocks. The accuracy of this model is evaluated against fully implemented architectures, showing that although it is three orders of magnitude faster than synthesis the error margin is very acceptable. The book concludes with a case study on a real System-on-Chip, including a RISC architecture, the Blocks CGRA and peripherals. Provides a comprehensive overview of many coarse-grained reconfigurable architectures (CGRAs) proposed in the last 25 years, as well as a classification of those CGRAs; Offers a new view on the positioning of CGRAs; Provides an in-depth description of structure of the Blocks CGRA and its unique aspects; Includes an extensive evaluation of various performance aspects of Blocks, such as performance, energy and area, as well as a comparison with various traditional approaches; Uses a case study showing how Blocks can be used in a real system on-chip, and how performance of this system-on-chip can be estimated using the proposed model.
650		0	_aEmbedded computer systems.
650		0	_aElectronic circuits.
650		0	_aMicroprocessors.
650		0	_aComputer architecture.
650	1	4	_aEmbedded Systems.
650	2	4	_aElectronic Circuits and Systems.
650	2	4	_aProcessor Architectures.
653		0	_aAdaptive computing systems
700	1		_aCorporaal, Henk. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
700	1		_aKumar, Akash. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
710	2		_aSpringerLink (Online service)
856	4	0	_uhttps://doi.org/10.1007/978-3-030-79774-4 _3Springer eBooks _zOnline access link to the resource
942			_2lcc _cEBK